Comments on: Microinstructions Done

By: Cody

Cody — Tue, 02 Apr 2013 00:25:29 +0000

Why do the ram control bits need to be inverted?

By: Cody

Cody — Fri, 08 Mar 2013 22:08:49 +0000

How would you add the compare command to your computer.

By: Kyle

Kyle — Sat, 02 Mar 2013 05:04:13 +0000

There are two blocks in the diagram, one for the instruction and one for the control word. The control word is 16 bits long and requires two 8-bit ROM chips. (I am assuming that you are talking about this diagram).

By: Cody

Cody — Sat, 02 Mar 2013 04:51:08 +0000

You said you used three rom chips, but there were only two in the diagram.

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By: Agneepath

Agneepath — Fri, 06 Jul 2012 21:03:13 +0000

This is very good amazing!

By: Manuel Neuer

Manuel Neuer — Thu, 05 Jul 2012 14:48:51 +0000

Very nice, orry for all of the questions, I’ve just started designing my own homebrew CPU partly based on your design and I’m trying to work out if there are any obvious things I’ve missed, so “Because I want to” is just as helpful an answer as something more technical

By: Kyle

Kyle — Sun, 13 May 2012 16:22:43 +0000

I have thought about that a lot. I bought a Z80 processor from them a while back as they were so inexpensive. If I ever were to delve into such a project, I now have the part.

By: Kyle

Kyle — Sun, 13 May 2012 16:20:28 +0000

It’s fine, ask as many questions as you like. What you are describing is what I was talking about in my previous comment. A variable machine cycle is when the control matrix detects when a NOP control word is present (by using an AND or NAND gate) and clears the ring counter so that the next instruction cycle can begin. I wish you luck with your project.

By: Chris

Chris — Sun, 13 May 2012 11:21:45 +0000

Is there a particular reason for wanting each op to take three T-states? As the fetch T-states are executed for every instruction, it effectively makes every op take 6 T-states, so reducing the Fetch to 2 T-states would reduce runtime by 16%. I guess you would want to burn off some more clock cycles for a NOP (for example if you are waiting for something to happen) because you would need three times as many NOP instructions in memory to get a 6-clock delay – I’m wondering if there is something else I’ve overlooked.

Sorry for all of the questions, I’ve just started designing my own homebrew CPU partly based on your design and I’m trying to work out if there are any obvious things I’ve missed, so “Because I want to” is just as helpful an answer as something more technical 🙂